DocumentCode :
3361237
Title :
Structural Tests for Jitter Tolerance in SerDes Receivers
Author :
Sunter, Stephen ; Roy, Aubin
fYear :
2006
fDate :
Oct. 2006
Firstpage :
1
Lastpage :
10
Abstract :
A suite of structural tests is described that uses on-chip under sampling to measure parameters that affect jitter tolerance in a multi-gigabit-per-second (Gbps) receiver. The tests measure high-frequency jitter (RMS value and histogram) in the received signal and in the recovered clock, plus transition-density dependent phase-shift, mean sampling position in the signal eye, sampling clock phase error, and pin-to-pin skew, all with near-picosecond resolution and repeatability, in tens of milliseconds. Hardware results for a 3 Gbps serializer/deserializer (SerDes) IC are included. The new method is suitable for an unlimited number of channels, it simplifies test hardware, it reduces production test time, and is suitable for any tester. The diagnostic capabilities facilitate improving yield and quality
Keywords :
automatic test equipment; clocks; production testing; receivers; timing jitter; 3 Gbit/s; SerDes receivers; high-frequency jitter; jitter tolerance; multigigabit-per-second receiver; on-chip sampling; pin-to-pin skew; sampling clock phase error; serializer/deserializer; structural tests; transition-density dependent phase-shift; Clocks; Hardware; Histograms; Jitter; Phase measurement; Position measurement; Production; Sampling methods; Signal resolution; Testing;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Test Conference, 2006. ITC '06. IEEE International
Conference_Location :
Santa Clara, CA
ISSN :
1089-3539
Print_ISBN :
1-4244-0292-1
Electronic_ISBN :
1089-3539
Type :
conf
DOI :
10.1109/TEST.2006.297726
Filename :
4079404
Link To Document :
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