Digital Measurement Technique for Capacitance Variation Detection on Integrated Circuit I/Os

A technique is required to detect capacitance variation on an integrated circuit I/O using only digital ASIC cells. A ring oscillator based design is investigated to make use of the well known property that its period varies linearly with capacitance. It is shown that a loaded ring oscillator does not behave as expected in some situations. Conditions for linear behavior are established. It is shown that the detection range of capacitance can be considerably improved with a sufficient delay into the ring or by imposing different voltage thresholds on the slowest ring oscillator node, as can be done with a Schmitt-trigger.