High-speed EBCOT with dual context-modeling coding architecture for JPEG2000

Author

Chiang, Jen-Shiun ; Chang, Chun-Hau ; Lin, Yu-Sen ; Hsieh, Chang-You ; Hsia, Chih-Hsien

Author_Institution

Dept. of Electr. Eng., Tamkang Univ., Taipei, Taiwan

Volume

3

fYear

2004

fDate

23-26 May 2004

Abstract

This work presents a parallel context-modeling coding architecture and a matching arithmetic coder (MQ coder) for the embedded block coding (EBCOT) unit of the JPEG2000 encoder. The tier-1 of the EBCOT consumes most of the computation time in a JPEG2000 encoding system, and the proposed parallel architecture can increase the throughput rate of the context-modeling. To match the high throughput rate of the parallel context-modeling architecture, and efficient pipelined architecture for context-based adaptive arithmetic encoder is proposed. This encoder of JPEG2000 can work at 185MHz to encode one symbol each cycle. Compared with the conventional context-modeling architecture, our parallel architecture can decrease the execution time about 25%.

Keywords

adaptive codes; arithmetic codes; data compression; image coding; parallel architectures; standards; 185 mHz; JPEG2000 encoding; adaptive arithmetic encoder; computation time; context-based arithmetic encoder; dual context-modeling coding; embedded block coding; high-speed EBCOT; matching arithmetic coder; parallel architecture; parallel context-modeling coding; pipelined architecture; throughput rate; Arithmetic; Block codes; Computer architecture; Context modeling; Discrete wavelet transforms; Image coding; Parallel architectures; Quantization; Throughput; Transform coding;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems, 2004. ISCAS '04. Proceedings of the 2004 International Symposium on

Print_ISBN

0-7803-8251-X

Type

conf

DOI

10.1109/ISCAS.2004.1328884

Filename

1328884