On the need for convergence between design validation and test

Summary form only given, as follows. High-level design languages and other design automation innovations have boosted designer productivity enabling designs which are more complex than ever before, allowing them to make full utilization of extra transistors afforded by Moore´s Law. However, these designs pose daunting challenges for pre- and post-silicon validation, and manufacturing test. Three dominant trends are rendering design and silicon validation an increasingly difficult task: increasing design complexity, inability to accurately model various design and manufacturing process parameters, and ever-shrinking time-to-market windows. As a result, deficiencies in design validation manifest themselves as bug escapes in silicon and an increasing number of the silicon failures are showing up only during system-level validation and test. The process of diagnosing and fixing failures at the system level is complex, ad hoc and error-prone and can have unacceptable delay in the ramp for high-volume manufacturing. This talk will explore the commonalities between pre- and post- design validation, and manufacturing test, and the need to create new capabilities that exploit the synergy between these domains to ease the task of validation while improving the manufacturing test quality.