Structural Testing of High-Speed Serial Buses: A Case Study Analysis

As the speed of serial buses breaks into multi-gigabits per second (Gb/S), current structural testing methodologies break down. Direct physical access to buses is becoming impossible due to board layout constraints. Even when access is achievable, the signal measured at the probe point may be significantly different than the signal received at the chip. In addition, when a probe can be placed on a test point, the added capacitance caused by the probe can distort the signal, masking design problems or reporting erroneous faults. Because these difficulties will only increase as bus speeds increase and as more buses lose physical access, engineers are faced with identifying alternative strategies for maintaining sufficient test coverage. Recognizing this situation, Intelreg developed a technology called Intelreg interconnect built-in self test (Intelreg IBIST) (Nejedlo, 2003 and Nejelo, 2003), which is being embedded into next-generation processors and chipsets. This case study examines the use of Intel IBIST to test circuit boards on an Intel based server. To perform the experiments, the Intel IBIST facilities were accessed via the board´s boundary-scan (IEEE 1149.1/JTAG) port. Data was gathered to validate fault detection and diagnostics. In addition, data generated by the experiment are compared with current methods of testing, such as probing with an oscilloscope