Title :
New Analog Test Metrics Based on Probabilistic and Deterministic Combination Approaches
Author :
Abderrahman, A. ; Sawan, M. ; Savaria, Y. ; Khouas, A.
Author_Institution :
Ecole Polytech. de Montreal Montreal, Montreal
Abstract :
The continuous characteristic of the parametric faults spectrum, the process variations and their masking effects are major difficulties limiting the development of efficient test generation for parametric faults. Moreover, there is a need for accurate test metrics to quantify the quality of a test set and to determine whether the testability is adequate. An analog test metric called parameter fault coverage (PFC) was recently introduced by the authors. The PFC metric takes into account the combination of the above major difficulties. In this paper, we consider parametric faults caused by the increased variance in device parameters. We introduce two novel metrics: one is called guaranteed parameter fault coverage (GPFC), which is the guaranteed lower bound of the PFC, and the other one is called partial parameter fault coverage (PPFC), which is the probabilistic component of the PFC. We combine the deterministic metric GPFC and the probabilistic metric PPFC to produce a PFC metric that enables accurately measuring the analog test quality and allows precisely measuring testability, thus avoiding the drawbacks of incorrect decisions regarding the use of design for testability (DFT) techniques. Also, we show that when DFT is used to improve circuit testability, PFC becomes dominated by the deterministic component GPFC, while the probabilistic component PPFC is minimized. This paper demonstrates the effectiveness of our approach on an illustrative example.
Keywords :
analogue circuits; circuit testing; design for testability; fault diagnosis; probability; analog test metrics; circuit testability; design for testability techniques; guaranteed parameter fault coverage; measuring testability; probabilistic-deterministic combination approaches; Analog circuits; Character generation; Circuit faults; Circuit testing; Costs; Design for testability; Electrical fault detection; Fault detection; Semiconductor device manufacture; Uncertainty;
Conference_Titel :
Electronics, Circuits and Systems, 2007. ICECS 2007. 14th IEEE International Conference on
Conference_Location :
Marrakech
Print_ISBN :
978-1-4244-1377-5
Electronic_ISBN :
978-1-4244-1378-2
DOI :
10.1109/ICECS.2007.4510936