The Economics of Implementing Scan Compression to Reduce Test Data Volume and Test Application Time

This paper presents an economic model that considers the full impact on test and manufacturing costs of on-chip compression circuits designed to reduce test data volume and test application time. The model unifies data and time reduction concepts, and describes how each component of test cost is affected by the compression level. It shows that profits for a given design are maximized at the compression level that minimizes the total costs of test. We calculate this optimal compression level for several example design scenarios to illustrate how designers can use the model to select the most cost-effective scan compression strategy