Clock distribution networks for 3-D ictegrated Circuits

Three-dimensional (3D) integration is an important technology that addresses fundamental limitations of on-chip interconnects. Several design issues related to 3D circuits, such as multi-plane synchronization, however, need to be addressed. A comparison of three 3D clock distribution network topologies is presented in this paper. Experimental results of a 3D test circuit manufactured by the MIT Lincoln Laboratories are also described. Successful operation of the 3D test circuit at 1.4 GHz is demonstrated. Clock skew and power dissipation measurements for the different clock topologies are also provided.