High Throughput Architecture for Forward Transforms Module of H.264/AVC Video Coding Standard

This paper presents a high throughput hardware architecture for forward transforms module of H.264/AVC video coding standard. The designed architecture can reach 303 MHz, when mapped to a Xilinx Virtex II Pro FPGA, and it is able to process 4.9 billion of samples per second. This throughput allows the use of the designed architecture in H.264/AVC codecs targeting real time when processing high resolution videos. This high throughput is very important to reduce the intra-prediction coding time, as will be explained in this paper. This architecture is able to process 1,561 HDTV 1080p frames per second. Comparing this design with published works was possible to conclude that this solution presents the best throughput among all other solutions.