FPGA-based implementation of a CFAR processor using Batcher´s sort and LUT arithmetic

This paper presents the realization of the forward automatic censored cell averaging detector (F-ACCAD), a novel CFAR algorithm for detecting targets in log-normal distribution clutter recently published . The algorithm is realized through an FPGA-based parallel architecture. The timing constraints of high resolution radar applications are considered and satisfied in the system. The sequential nature of the algorithm has been parallelized to achieve the desired processing delay. The intensive statistical calculations and the complexity of the algorithm have been significantly reduced by using lookup tables (LUTs). Batcher´s sort, a parallel sorting algorithm, is adopted in this work. The hardware synthesis results and timing analysis are reported at the end.