• DocumentCode
    3361802
  • Title

    SOC and Multicore Debug: Are Design for Debug (DFD) Features that Are Put in Re-use Cores Sufficient for Silicon Debug?

  • Author

    Gottlieb, Bob

  • Author_Institution
    Intel Corp., Santa Clara, CA
  • fYear
    2006
  • fDate
    Oct. 2006
  • Firstpage
    1
  • Lastpage
    1
  • Abstract
    While reuseable cores and SOC components are delivered along with a "complete" test suite to ensure good functional test coverage, this is inadequate for silicon debug
  • Keywords
    design for testability; system-on-chip; design for debug; functional testing; multicore chips; reuseable cores; silicon debug; system-on-chip; Automatic testing; Circuit testing; Design for disassembly; Design for testability; Educational institutions; Logic arrays; Logic circuits; Logic testing; Multicore processing; Silicon;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Test Conference, 2006. ITC '06. IEEE International
  • Conference_Location
    Santa Clara, CA
  • ISSN
    1089-3539
  • Print_ISBN
    1-4244-0292-1
  • Electronic_ISBN
    1089-3539
  • Type

    conf

  • DOI
    10.1109/TEST.2006.297761
  • Filename
    4079439
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=3361802