A 159.2mW SoC implementation of T-DMB receiver including stacked memories

This paper describes a system on chip (SoC) implementation of terrestrial digital multimedia broadcasting (T-DMB) receiver which integrates RF tuner, analog to digital converter (ADC), baseband processor, and multimedia processor in single silicon wafer. The pseudo-SRAM (PSRAM) and SDRAM are doubly stacked with method of silicon in package (SIP). A low-IF RF tuner and a 10 bits pipelined ADC is used in this work as IP cores. Baseband processor contains Eureka-147 digital audio broadcasting (DAB) modem, MPEG1-Layer2 decoder, and outer decoder for T-DMB. Multimedia processor is consists of 32 bit embedded micro processor, 24 bit fixed-point DSP, and H.264/AVC hardware core. The T-DMB SoC was fabricated by using 0.13 um 1 poly 8 metal (1P8M) CMOS process and it gives successful performance of 159.2 mW total power dissipation including PSRAM and SDRAM at supply voltages of 1.2 V, 2.5 V for core and I/O respectively.