Digital on-chip phase noise measurement

Author

Ouda, Mahmoud ; Hegazi, Emad ; Ragai, Hany F.

Author_Institution

Dept. of Electron. & Commun., Ain Shams Univ., Cairo, Egypt

fYear

2009

fDate

15-17 Nov. 2009

Firstpage

1

Lastpage

5

Abstract

In this paper, we propose an all-digital on-chip phase noise measurement technique. This Technique can be integrated as part of a built-in self-test (BIST) scheme for phase-locked loop (PLL)-based clock synthesizers. The proposed technique based on an all digital Â¿Â¿-frequency discriminator (Â¿Â¿FD). Unlike all previously reported techniques, our proposed technique is implemented using digital-only circuits. This makes it easily integrated and scaled down for high-density microprocessor applications with modern sub 100 nm technology nodes.

Keywords

built-in self test; microprocessor chips; noise measurement; phase locked loops; phase noise; BIST scheme; built-in self-test scheme; clock synthesizers; digital on-chip phase noise measurement; digital-only circuits; high-density microprocessor applications; phase-locked loop; Â¿Â¿-frequency discriminator; Built-in self-test; Circuits; Clocks; Measurement techniques; Microprocessors; Noise measurement; Phase locked loops; Phase measurement; Phase noise; Synthesizers; All digital PLL (AD-PLL); PLL; phase domain; phase noise; sigma delta frequency discriminator (ΣΔFD); voltage-controlled oscillator (VCO);

fLanguage

English

Publisher

ieee

Conference_Titel

Design and Test Workshop (IDT), 2009 4th International

Conference_Location

Riyadh

Print_ISBN

978-1-4244-5748-9

Type

conf

DOI

10.1109/IDT.2009.5404090

Filename

5404090