Title :
FPGA-Based Implementation of RAM with Asymmetric Port Widths for Run-Time Reconfiguration
Author :
Senhadji-Navarro, R. ; García-Vargas, I. ; Jiménez-Moreno, G. ; Civit-Balcells, A.
Author_Institution :
Univ. de, Sevilla
Abstract :
In this paper, we present a HDL description of a RAM with asymmetric port widths which allows read and write operations with different data size. This RAM is suitable for implementing run-time reconfigurable systems in FPGA. The proposed RAM specification has been tested with different target devices.
Keywords :
field programmable gate arrays; hardware description languages; random-access storage; FPGA; HDL description; RAM; asymmetric port widths; run-time reconfiguration; Circuits; Clocks; Field programmable gate arrays; Hardware design languages; Programmable logic arrays; Random access memory; Read-write memory; Runtime; Table lookup; Testing;
Conference_Titel :
Electronics, Circuits and Systems, 2007. ICECS 2007. 14th IEEE International Conference on
Conference_Location :
Marrakech
Print_ISBN :
978-1-4244-1377-5
Electronic_ISBN :
978-1-4244-1378-2
DOI :
10.1109/ICECS.2007.4510959
