High-Speed I/O Tests in High-Volume Manufacturing

There is a rapidly growing trend of chips across multiple market segments using high speed IOs. Significant improvements in CMOS technology have enabled chipmakers to incorporate these high speed IOs into an increasing number of high-volume devices beyond the traditional communications segment and into the microprocessor, ASIC and system on chip (SOC) segments. As such, the test development and ATE (automated test equipment) worlds face mounting pressure to come up with increasingly complex and innovative test solutions that, at the same time, must keep the costs down in order to be viable for high volume manufacturing (HVM). This panel will address some of the key challenges facing high speed IO testing in HVM and suggest possible directions that will be a combination of ATE design and on-chip DFT techniques