Title :
How to design an effective Serial Input Shift Register (SISR) for data compression process of Built-In Self-Test methodology
Author :
Ahmad, A. ; Jaber, A.-B.
Author_Institution :
Dept. of Electr. & Comput. Eng., Sultan Qaboos Univ., Muscat, Oman
Abstract :
This paper investigates the impact of characteristic polynomial on an effective design of Serial Input Shift Register (SISR). How the use of a primitive characteristic polynomial cannot cope with the minimization of aliasing error probability. Further, the paper also, suggests about the selection of characteristic polynomial to minimize hardware, power dissipation and test data compression time. The study of this paper is based on simulation study using a suitably developed tool.
Keywords :
built-in self test; error statistics; polynomials; shift registers; built-in self-test methodology; characteristic polynomial; data compression process; error probability; hardware minimization; power dissipation; serial input shift register; test data compression time; Built-in self-test; Circuit faults; Circuit testing; Costs; Data compression; Design for testability; Hardware; Polynomials; Shift registers; System-on-a-chip; Aliasing error; Built-In Self-Test; Characteristic polynomial; Circuit Under Test; Design For Testability; Linear Feedback Shift Registers; Primitive polynomial; Serial Input Shift Register; System on Chip;
Conference_Titel :
Design and Test Workshop (IDT), 2009 4th International
Conference_Location :
Riyadh
Print_ISBN :
978-1-4244-5748-9
DOI :
10.1109/IDT.2009.5404091
