DocumentCode
3361872
Title
Advances in Multi-Gate MOSFET Circuit Design
Author
Fulde, M. ; Arnim, K.v. ; Pacha, C. ; Bauer, F. ; Russ, C. ; Siprak, D. ; Xiong, W. ; Marshall, A. ; Cleavelin, C.R. ; Schruefer, K. ; Schmitt-Landsiedel, D. ; Knoblinger, G.
Author_Institution
Infineon Technol. AG, Villach
fYear
2007
fDate
11-14 Dec. 2007
Firstpage
186
Lastpage
189
Abstract
In this paper recent advances in Multi-Gate MOS-FET (MuGFET) circuit design are reported. The feasibility of essential parts of low-power mobile SoC applications and large scale integration capability is shown. Excellent short channel control enables undoped metal gate MuGFETs to outperfom their planar counterparts in terms of delay-leakage trade-off. Superior voltage scaling efficiency and competitive performance is demonstrated for a product typical critical path. Design and layout optimization for improved SRAM cell stability is shown. Beneficial analog performance is exemplary demonstrated for an OpAmp. A potential degradation of ADC performance due to transient VT mismatch is shown, the use of redundancy is proposed as countermeasure. Key RF building blocks are presented, MuGFET specific design issues are outlined. A comparison of different ESD elements yields a potential ESD protection scheme combining planar and MuGFET devices.
Keywords
MOSFET; SRAM chips; integrated circuit design; operational amplifiers; system-on-chip; OpAmp; SRAM cell stability; delay-leakage trade-off; low-power mobile SoC; multi-gate MOSFET circuit design; Circuit synthesis; Degradation; Delay; Design optimization; Electrostatic discharge; Large scale integration; MOSFET circuits; Random access memory; Stability; Voltage;
fLanguage
English
Publisher
ieee
Conference_Titel
Electronics, Circuits and Systems, 2007. ICECS 2007. 14th IEEE International Conference on
Conference_Location
Marrakech
Print_ISBN
978-1-4244-1377-5
Electronic_ISBN
978-1-4244-1378-2
Type
conf
DOI
10.1109/ICECS.2007.4510961
Filename
4510961
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