Title :
What Trends are Emerging in Microprocessor Test as CMT Architecture Scales SERDES IO to 100% Interconnect?
Author_Institution :
Sun Microsyst., Sunnyvale, CA
Abstract :
The multi-core microprocessors are driving IO architecture to 100% SERDES across the processors´ memory, network and system IO interfaces. This scale of SERDES integration is that traditional DFT approaches adequately screen for functional verification of the IO macros and some amount of PHY parametrics, but fall short when used to test an integrated product with >200, 4.8 Gb/s lanes. Detailed AC parametric margin testing is still necessary to achieve adequate defect coverage
Keywords :
design for testability; microprocessor chips; PHY parametrics; SERDES testing; defect coverage; design for testability; functional verification; margin testing; microprocessors test; Bandwidth; Circuit testing; Costs; Design for testability; Jitter; Microprocessors; Observability; Semiconductor device measurement; Test equipment; Throughput;
Conference_Titel :
Test Conference, 2006. ITC '06. IEEE International
Conference_Location :
Santa Clara, CA
Print_ISBN :
1-4244-0292-1
Electronic_ISBN :
1089-3539
DOI :
10.1109/TEST.2006.297766
