Role of Test in Yield Learning for 65nm and Beyond

Only recently it has become pretty clear that back-end technologies can no longer be seen as an independent operation or as an after-thought. Specifically the "test" arena is changing dramatically from a pure good/bad decision maker towards a key information provider on the product e.g. on the manufacturing process. This enhanced test data contributes, or even drives, following yield and quality improvement actions. To be able to do so the test data is next linked with internal wafer fab (in-line) data, as well as with specific design information like layout structures. From the resulting defect pareto it can be decided to either take action on the (manufacturing) process (in the wafer fab), or towards the design area. The latter may then lead to enhanced design for manufacturing rules or in changing parameters like timing or power margins. This then, ideally, closes the loop between manufacturing and design