DocumentCode :
3362039
Title :
A Predominant Routing for on-chip networks
Author :
Asad, Arghavan ; Seyrafi, Mehrdad ; Zonouz, Amir Ehsani ; Soryani, Mohsen ; Fathy, Mahmood
Author_Institution :
Fac. of Comput. Eng., Iran Univ. of Sci. & Technol., Tehran, Iran
fYear :
2009
fDate :
15-17 Nov. 2009
Firstpage :
1
Lastpage :
6
Abstract :
It is necessary to suppress the average delay to low when a packet is forwarded from a source node to a destination node in network-on-chip (NoC) for the quality maintenance of the communication between nodes. Routing algorithms have a prominent impact on communication quality and performance in on chip interconnection networks. In this paper, we present a novel routing method called Predominant Routing which can select the best route for communication flows using a simple setup network. In the setup network time, a number of low-latency virtual point-to-point connections are provided to construct the best route at run time when a new flow (a connection between a source and its destination to carry messages) is detected. Evaluation results show that the proposed routing algorithm consumes low power and approach to extremely low latency in packet switched networks-on-chip.
Keywords :
network routing; network-on-chip; packet switching; NoC; Predominant Routing; average delay; network-on-chip; packet switching; routing algorithms; Adaptive systems; Computer networks; Delay; Multiprocessor interconnection networks; Network-on-a-chip; Packet switching; Power system economics; Routing; Switches; System-on-a-chip; Adaptive Routing; Deterministic Routing; Networks on Chip (NoC); on-Chip Interconnection Networks;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Design and Test Workshop (IDT), 2009 4th International
Conference_Location :
Riyadh
Print_ISBN :
978-1-4244-5748-9
Type :
conf
DOI :
10.1109/IDT.2009.5404103
Filename :
5404103
Link To Document :
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