Exploring multistage interconnection network implementations for FPGA-based MPSOCs

Modern embedded systems integrated a variety of complex and heterogeneous components communicating with each other at high-speed rates. The interconnection architecture employed in such systems has an important impact to their overall performance. Multistage interconnection network has emerged as a promising alternative to ensure communication for multiprocessor system on chips. In this paper, we describe a design methodology of MIN-based MPSoC on programmable circuits (FPGAs). As a case study, we propose an evaluation methodology based on performance metrics that include latency, execution time and area requirements for two MIN-based MPSOC topologies, i.e. the omega and the butterfly fat tree (BFT). Moreover, we show in our experimental results that multistage interconnection networks will become a future general purpose interconnect for FPGA-based MPSOCs much like today´s standard bus architectures.