Title :
Automatic Generation of VHDL Code for Self-Timed Circuits from Simulink Specifications
Author :
Tranchero, Maurizio ; Reyneri, Leonardo M.
Author_Institution :
Politecnico di Torino, Turin
Abstract :
This paper introduces a methodology for using self-timed logic in FPGA-based embedded systems starting from a high-level specification of data-flow networks. It uses CodeSimulink as an environment for code generation. The asynchronous circuits are synthesized using conventional commercial tools and we propose solutions for the issues raised. Also we describe a simple way of simulating these designs.
Keywords :
asynchronous circuits; field programmable gate arrays; hardware description languages; logic circuits; CodeSimulink; FPGA-based embedded systems; Simulink specifications; VHDL code; asynchronous circuits; automatic generation; code generation; data-flow networks; high-level specification; self-timed circuits; Asynchronous circuits; Circuit simulation; Circuit synthesis; Clocks; Embedded system; Energy consumption; Field programmable gate arrays; Signal generators; Signal synthesis; Timing;
Conference_Titel :
Electronics, Circuits and Systems, 2007. ICECS 2007. 14th IEEE International Conference on
Conference_Location :
Marrakech
Print_ISBN :
978-1-4244-1377-5
Electronic_ISBN :
978-1-4244-1378-2
DOI :
10.1109/ICECS.2007.4510986
