Simulation of Voice Processing Applications through VLIW DSP Architectures

This paper presents simulation of G.729a speech codec, as a compute-intensive voice processing application, on a VLIW DSP architecture. The simulator of target processor is verified by the Texas Instruments C62xx VLIW DSP architecture. The cycle-accurate simulator is implemented using C++ programming language. The G.729a reference code is modified for single- and multi-channel voice coding and is executed in the simulation environment. The experiments are performed for two modes: single and multiple channels of voice data. The obtained results demonstrate functionality of the VLIW DSP architecture for efficient evaluation of single- and multi-channel voice processing. It is achieved that the target processor is functionally available to support real-time execution of up to 10 voice channels at the 200 MHz working frequency while considering all of the operating conflicts.