Clustering techniques for improving transient current testing

Several techniques are used to detect defects in digital integrated circuits. Among these techniques is transient current testing (i_DDT). The detection capability of i_DDT degrades as the size and switching activity of the circuit under test (CUT) increases. In this paper we present clustering techniques that control the switching activity of one cluster in response to applied test vector-pairs. Our clustering techniques take into consideration the physical layout of the gates in the CUT. This paper shows the results of the clustering techniques when applied to ISCAS benchmark circuits and verify, using circuit simulation, the ability of the techniques in improving defect detection capabilities of i_DDT-based testing.