Rapid Prototyping IP for Autocorrelation Computation

The paper presents a methodology toward a heterogeneous implementation of popular voice codec algorithms. The main focus is towards code speed up. The renewed interest in such implementation is typically driven by the use of reusable components IPs (Intellectual Property). In this context we present the design of a voice decoder dedicated to embedded systems. For our prototyping design, the system has been built around, on the one hand an FPGA (Field programmable gate array) to achieve the so called IP hardware part - the autocorrelation computation, and on the other hand a DSP (Digital Signal Processors) for the remainder of the algorithm. The IP design interest is discussed and implementation results are presented.