DocumentCode :
3362380
Title :
An integrated ESD design verification flow
Author :
Hegazy, Hazem
Author_Institution :
Mentor Graphics, Cairo, Egypt
fYear :
2009
fDate :
15-17 Nov. 2009
Firstpage :
2
Lastpage :
4
Abstract :
In this paper, ESD verification challenges are addressed from an EDA perspective. These challenges are typically layout dependant however; they are implicitly design topology related. Moreover, design sizes and complexity of multiple power domains trigger the need for an EDA design verification flow that substantiates ESD design rule checking.
Keywords :
electrostatic discharge; network synthesis; design topology; electrostatic discharge; integrated ESD design; verification flow; Atherosclerosis; Circuit topology; Clamps; Current density; Electronic design automation and methodology; Electrostatic discharge; Graphics; Integrated circuit interconnections; Layout; Protection;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Design and Test Workshop (IDT), 2009 4th International
Conference_Location :
Riyadh
Print_ISBN :
978-1-4244-5748-9
Type :
conf
DOI :
10.1109/IDT.2009.5404125
Filename :
5404125
Link To Document :
بازگشت