A Transmission Line Modelling VLSI processor designed with a novel Electronic System Level Methodology

This paper discusses the development of a high performance, System-on-Chip (SoC) Transmission Line Modeling (TLM) accelerator designed using novel Electronic System-Level (ESL) flows, from reference C sources. The TLM processor includes a silicon implementation of the 32-bit subset of the IEEE 754 floating point standard, originally part of the Softfloat library. The Floating point core is used extensively in the numerical calculations of the TLM code whereas multiple embedded SRAM components are utilized for array variable storage. Post-behavioral-synthesis, cycle-accurate simulations show a three orders-of-magnitude better runtime performance compared to the reference C code executing on a 100 MHz, 32-bit ASIC processor. At the same time, the TLM processor exhibits greater than 150× performance compared to a 4-way, 200 MHz, 32-bit Chip-multiprocessor CMP). There results clearly demonstrate the potential of ESL methodologies for accelerating compute-intensive applications, compared to programmable solutions. The proposed ESL-based architecture is applicable to a range of guided and radiated wave problems and is validated in models of a WR-90 waveguide