A delay-aware topology-based design for Networks-on-Chip applications

Network delay is a major design parameter for Networks-on-Chip (NoC)-based applications. Improving NoC delay could be achieved at different design phases. At the system level, we study in this paper the impact of the network topology on NoC system delay using graph-theoretic concepts. A topology-based model is developed to calculate the average NoC delay, which is caused by links and routers. The proposed model could be used to select the optimal topology that achieves the minimum network delay for a given NoC application. A case study is presented to show how this model could be used to improve the delay of a given NoC application at early design phases.