Phase Locked Loop gain shaping for gigahertz operation

The paper presents a novel concept of gain shaping in charge-pump based Phase Locked Loops. The gain shaping involves processing ICO control current in two parallel paths of low and high frequency. By effectively lowering VCO gain at high frequencies, as compared to a standard design, larger immunity to noise sources is obtained. The gain shaping block introduces additional zero and pole in the PLL transfer characteristics. The resulting Type IV PLL has been designed for 2.5 GHz operation for applications in wireline communication (SONET/SDH systems), storage (Infiniband protocol) and PC interfacing (PCI-Express I/O). A new phase-frequency detector with zero dead zone was introduced. Standard VCO consisting of four stages implemented in a differential current-mode logic (CML) was used. The chip has been implemented in 0.18 μm CMOS process, dissipates 92 mW from a 1.8 V power supply. It offers over three-fold improvement in power supply rejection ratio (PSRR) compared to the standard Type III PLL.