Low Power and Stable FinFET SRAM with Static Independent Gate Bias for Enhanced Integration Density

Data stability of Static Random Access Memory (SRAM) circuits has become an important issue with the scaling of CMOS technology. Memory arrays are also an important source of leakage since the majority of transistors are utilized for on-chip caches in today´s high performance microprocessors. A six transistor (6T) SRAM cell based on independent-gate FinFET technology (IG-FinFET) is described in this paper for simultaneously reducing the active and standby mode power consumption while enhancing the data stability and the integration density. With the independent-gate FinFET SRAM cell, the back gates of the access transistors are permanently disabled in order to enhance the data stability. The back gates of the pull-up FinFETs in the cross-coupled inverters are also permanently disabled to achieve write ability. Functionality and sufficient read stability are achieved with minimum sized transistors with the independent-gate-bias technique. The IG-FinFET SRAM cell reduces the idle mode leakage power, the active mode read power, the active mode write power, the write delay, and the cell area by up to 36%, 26%, 24%, 20%, and 12.4%, respectively, as compared to a standard tied-gate FinFET SRAM cell with similar read static-noise-margin in a 32nm FinFET technology.