A cost-effective parallel architecture for the CodeRAKE receiver

The receiver architecture in the third generation communication systems should be configurable according to the number of channels and codes per users. Additionally, the receiver architecture should support high bit rates. To achieve this goal, different RAKE architectures have been designed for this propose. In this paper, we propose a parallel multi-path architecture for the CodeRAKE receiver. It has improved bit rates with a suitable area consumption compared to the other architectures. The proposed approach allows parallel processing of chips from all the multiple propagation paths on a highly regular architecture.