Title :
A realistic fault simulation model for EEPROM memories
Author :
Aziza, H. ; Plantier, J. ; Portal, J.-M.
Author_Institution :
IM2NP, IMT - Technopole de Chateau Gombert, Marseille, France
Abstract :
In this paper, a list of faults is injected in an elementary memory array circuit. Electrical simulation results show impact of each fault on EEPROM cells logical values and threshold voltages. Results are analyzed and fault coverage of EEPROM memories standard test patterns is evaluated.
Keywords :
EPROM; fault simulation; memory architecture; EEPROM memories; elementary memory array circuit; fault simulation model; logical values; threshold voltage; Circuit faults; Circuit simulation; Circuit testing; EPROM; Fabrication; Geometry; Nonvolatile memory; Solid modeling; Threshold voltage; Tunneling; EEPROM; electrical simulation; fault coverage; test;
Conference_Titel :
Design and Test Workshop (IDT), 2009 4th International
Conference_Location :
Riyadh
Print_ISBN :
978-1-4244-5748-9
DOI :
10.1109/IDT.2009.5404158
