Design guidelines of vertical surrounding gate (VSG) MOSFETs for future ULSI circuit applications

Author

Kranti, A. ; Rashmi ; Haldar, S. ; Gupta, R.S.

Author_Institution

Dept. of Electron. Sci., Delhi Univ., India

fYear

2001

fDate

14-14 Sept. 2001

Firstpage

161

Lastpage

165

Abstract

This paper discusses the device design of vertical surrounding gate (VSG) MOSFETs. Poisson´s equation is solved using a Laplace reduction technique and Bessel functions to predict the device characteristics. The concept of inverse natural/characteristic length (/spl gamma/) and critical length (L/sub critical/) is developed, which serves as a tool for device optimization for improved performance. Results thus obtained are in close proximity with published data available in the literature.

Keywords

Bessel functions; Laplace equations; MOS integrated circuits; MOSFET; Poisson equation; ULSI; optimisation; semiconductor device models; Bessel functions; Laplace reduction technique; Poisson´s equation; ULSI circuit applications; VSG MOSFETs; critical length; design guidelines; device characteristics; device design; device optimization; inverse natural/characteristic length; vertical surrounding gate MOSFETs; Circuits; Doping; Guidelines; Large scale integration; MOSFETs; Poisson equations; Rain; Silicon on insulator technology; Threshold voltage; Ultra large scale integration;

fLanguage

English

Publisher

ieee

Conference_Titel

Silicon Monolithic Integrated Circuits in RF Systems, 2001. Digest of Papers. 2001 Topical Meeting on

Conference_Location

Ann Arbor, MI, USA

Print_ISBN

0-7803-7129-1

Type

conf

DOI

10.1109/SMIC.2001.942359

Filename

942359