Parasitic barrier effects in SiGe HBTs due to p-n junction displacement

Author

Mathur, N. ; Todorova, D. ; Roenker, K.P.

Author_Institution

Dept. of Electr. & Comput. Eng. & Comput. Sci., Cincinnati Univ., OH, USA

fYear

2001

fDate

14-14 Sept. 2001

Firstpage

177

Lastpage

186

Abstract

The effects of displacement of the p-n junction with respect to the SiGe-Si heterojunction at both the emitter and collector junctions have been studied using a commercial numerical device simulator. Parasitic barrier formation at both junctions has been quantified and their degrading effects on HBT performance investigated as a function of junction displacement and bias. The effectiveness of changes in the device´s structure, such as the insertion of an n+ launcher layer at the collector junction, has been investigated in order to reduce device sensitivity to p-n junction displacement while maintaining device performance.

Keywords

Ge-Si alloys; heterojunction bipolar transistors; numerical analysis; p-n junctions; semiconductor device models; semiconductor materials; HBT performance degradation; SiGe HBTs; SiGe-Si; SiGe-Si heterojunction; collector junction; device performance; device sensitivity; device structure; emitter junction; junction bias; junction displacement; n+ launcher layer insertion; numerical device simulator; p-n junction; p-n junction displacement; parasitic barrier effects; parasitic barrier formation; Analytical models; Computer science; Degradation; Doping; Germanium silicon alloys; Heterojunction bipolar transistors; Numerical simulation; P-n junctions; Silicon germanium; Temperature;

fLanguage

English

Publisher

ieee

Conference_Titel

Silicon Monolithic Integrated Circuits in RF Systems, 2001. Digest of Papers. 2001 Topical Meeting on

Conference_Location

Ann Arbor, MI, USA

Print_ISBN

0-7803-7129-1

Type

conf

DOI

10.1109/SMIC.2001.942362

Filename

942362