Title :
A More Effective Ceff for Slew Estimation
Author :
Zhou, Ying ; Li, Zhuo ; Kanj, Rouwaida N. ; Papa, David A. ; Nassif, Sani ; Shi, Weiping
Author_Institution :
Texas A&M Univ., College Station
fDate :
May 30 2007-June 1 2007
Abstract :
Accurate chip level timing analysis requires a careful modeling of interaction between logic drivers and interconnect wires. Existing static-timing analysis methodologies translate the actual loading and interconnect parasitics into a single effective capacitance. However, previous approaches to perform that translation capture the delay information only. They are not able to capture the slew information at the output of logic drivers, which results in unnecessary inaccuracy for static timing analysis. This paper presents a new accurate and simple closed-form approach to compute the effective capacitance and model the slew rate at the signal output more accurately. Our approach is especially suitable for the chip level timing analysis at the early stage of design.
Keywords :
delays; integrated circuit design; integrated circuit interconnections; integrated circuit modelling; log normal distribution; logic circuits; capacitance; chip level timing analysis; delay; interconnect wires; logic drivers; slew estimation; static-timing analysis; Capacitance; Delay effects; Delay estimation; Integrated circuit interconnections; Iterative methods; Logic; Propagation delay; Propagation losses; SPICE; Timing;
Conference_Titel :
Integrated Circuit Design and Technology, 2007. ICICDT '07. IEEE International Conference on
Conference_Location :
Austin, TX
Print_ISBN :
1-4244-0757-5
Electronic_ISBN :
1-4244-0757-5
DOI :
10.1109/ICICDT.2007.4299530