Title :
A CMOS 10 Gb/s clock and data recovery circuit with a novel adjustable Kpd phase detector
Author :
Chen, Xinyu ; Green, Michael M.
Author_Institution :
Dept. of Electr. Eng. & Comput. Sci., California Univ., Irvine, CA, USA
Abstract :
A clock and data recovery (CDR) circuit for 10 Gb/s broadband communication using a CMOS process is presented. The circuit makes use of a novel adjustable Kpd phase detector. The phase detector can provide a binary characteristic or a linear characteristic under different control voltages. The CDR core circuit consists of a phase frequency detector, an integrator, a LC VCO and a low pass filter provided off-chip. Two more phase detectors, a bang-bang phase detector and a Hogge phase detector, are also built in the circuit for performance comparison.
Keywords :
CMOS analogue integrated circuits; broadband networks; integrated circuit design; integrating circuits; low-pass filters; phase detectors; synchronisation; timing jitter; voltage-controlled oscillators; 10 Gbit/s; CMOS clock recovery circuit; CMOS data recovery circuit; Hogge phase detector; Kpd phase detector; LC VCO; bang-bang phase detector; broadband communication; clock-data recovery core circuit; integrator; low pass filter; phase frequency detector; Broadband communication; CMOS process; Circuits; Clocks; Communication system control; Low pass filters; Phase detection; Phase frequency detector; Voltage control; Voltage-controlled oscillators;
Conference_Titel :
Circuits and Systems, 2004. ISCAS '04. Proceedings of the 2004 International Symposium on
Print_ISBN :
0-7803-8251-X
DOI :
10.1109/ISCAS.2004.1329000
