Generation of the Optimal Bit-Width Topology of the Fast Hybrid Adder in a Parallel Multiplier

In state-of-the-art Digital Signal Processing (DSP) and Graphics applications, multiplication is an important and computationally intensive operation, consuming a significant amount of delay. The final carry propagate hybrid adder inside a multiplier plays an important role in determining the performance of the multiplication block. This paper presents an algorithmic approach to generate the optimal bit-width configuration of each of the sub-adders present inside the hybrid adder. Our technique is useful in selecting the best configuration (out of a large number of possible configurations) of the hybrid adder, thereby improving the overall performance of the chip. Our experiments involve different combinations of designs, technology libraries and timing constraints, and the results show that our algorithm successfully predicts the best hybrid-adder topology with a very low runtime.