Four-Terminal FinFET Device Technology

Author

Masahara, M. ; Endo, K. ; Liu, Y.X. ; O´uchi, S. ; Matsukawa, T. ; Surdeanu, R. ; Witters, L. ; Doornbos, G. ; Nguyen, V.H. ; Van den Bosch, G. ; Vrancken, C. ; Jurczak, M. ; Biesemans, S. ; Suzuki, E.

Author_Institution

Nat. Inst. of AIST, Tsukuba

fYear

2007

fDate

May 30 2007-June 1 2007

Firstpage

1

Lastpage

4

Abstract

One of the biggest challenges for the VLSI circuits with 32-nm-technology nodes and beyond is to overcome the issue of catastrophic increases in power consumption due to short-channel effects (SCEs). Fortunately, "independent" double-gate (DG) FinFETs (named "4-terminal-FinFET" because of its four terminals; source, drain, gate 1 and gate 2) have a promising potential to overcome this issue thanks to a post-fabrication flexible V_th controllability in addition to their superior SCE immunity. This paper presents novel 4T-FinFET device technology based on experimental demonstrations. Newly-developed DG separation processes for the 4T-FinFETs, successful fabrication of the optimum 4T-FinFET with asymmetric gate oxides, and dynamic power management demonstration using 4T-FinFET are presented.

Keywords

MOSFET; VLSI; VLSI circuits; asymmetric gate oxides; dynamic power management; four-terminal FinFET device; independent double-gate FinFET; short-channel effects; size 32 nm; Circuit optimization; Controllability; Energy consumption; Energy management; Etching; Fabrication; FinFETs; Separation processes; Thickness control; Very large scale integration; 4T-FinFET; asymmetric gate oxide thickness; double gate separation; dynamic power management; flexible Vth control;

fLanguage

English

Publisher

ieee

Conference_Titel

Integrated Circuit Design and Technology, 2007. ICICDT '07. IEEE International Conference on

Conference_Location

Austin, TX

Print_ISBN

1-4244-0757-5

Electronic_ISBN

1-4244-0757-5

Type

conf

DOI

10.1109/ICICDT.2007.4299542

Filename

4299542