JTAG debug tool for efficient debugging on V93K

The JTAG protocol is used extensively in testing today´s complex IC devices. It is used to access DFT structures and many other configuration registers in the device. JTAG sequences are used to configure the device in certain modes before test and to obtain information after test. Test engineers needs to learn DFT structure and how to configure the settings to test the device correctly. This “learning” is usually done in real-time on the tester by trial and error, seeing how the device responds as bits are flipped in the configuration registers. This learning involves developing JTAG patterns for all different configurations the engineer wishes to try. It is a process in which the JTAG patterns can change frequently until the right settings are obtained. The time delay for bringing a new JTAG pattern into the test program can be quite costly if the conversion/compiling from STIL to BINL is long: every change or mistake made in the JTAG pattern can translate into hours. Though there are advanced tester tools such as protocol-aware readily available on the Advantest 93K tester platform (referred as V93K in this article), the existing EDA outputs cannot be leveraged without building registers sequence by sequence. We developed a JTAG debug tool on V93K to address this time delay for bringing a new JTAG pattern into an already-loaded test program. The tool has the ability to copy the STIL content directly into the tester vector memory without any delay for conversion to BINL. The tool also takes care of creating pattern burst dynamically, executing and reporting functional test results. The debugged patterns can be used directly for a production run. This tool also can be applied to any other protocol without modification. This paper details the steps used in developing this tool and explains its functionality.