DocumentCode
3363506
Title
Multi-level logic minimization through fault dictionary analysis
Author
Mehler, Ronald W. ; Mercer, M. Ray
Author_Institution
Texas Univ., Dallas, TX, USA
fYear
1999
fDate
1999
Firstpage
315
Lastpage
318
Abstract
Presents the results of the study of a new algorithm for multi-level logic minimization. The study is based on the premise that an untestable node is a redundant node, and that nodes that do not demonstrably cause conflicting behavior at primary outputs may be compatible. Data gathered using the presented techniques show that fault dictionary analysis is a powerful tool for logic minimization. The algorithm developed in this study, the Texas Aggies Logic Optimizing Netlister (TALON), is shown to be competitive with, and complementary to, other methodologies. TALON can be used by itself or as a preprocessor or postprocessor for other tools, giving superior results to those obtained by any of them working independently
Keywords
dictionaries; fault diagnosis; logic CAD; minimisation of switching nets; TALON algorithm; Texas Aggies Logic Optimizing Netlister; compatible nodes; conflicting behavior; fault dictionary analysis; multi-level logic minimization; postprocessor; preprocessor; primary outputs; redundant node; untestable node; Automatic test pattern generation; Circuit faults; Circuit simulation; Circuit testing; Dictionaries; Electrical fault detection; Fault detection; Logic; Minimization; Test pattern generators;
fLanguage
English
Publisher
ieee
Conference_Titel
Computer Design, 1999. (ICCD '99) International Conference on
Conference_Location
Austin, TX
ISSN
1063-6404
Print_ISBN
0-7695-0406-X
Type
conf
DOI
10.1109/ICCD.1999.808558
Filename
808558
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