• DocumentCode
    3363521
  • Title

    Wafer reconstruction: An alternative 3D integration process flow

  • Author

    Teng Wang ; Silva, J.L. ; Daily, R. ; Capuz, G. ; Gonzalez, M. ; June Rebibis, Kenneth ; Kroehnert, Steffen ; Beyne, Eric

  • Author_Institution
    imec, Leuven, Belgium
  • fYear
    2013
  • fDate
    11-13 Dec. 2013
  • Firstpage
    415
  • Lastpage
    419
  • Abstract
    Wafer reconstruction is a process of forming an integral handle-able wafer by filling the gaps between the dies after die-to-wafer assembly to allow for further processing on the landing wafer, e.g. thinning, redistribution layer deposition, and bumping. This paper examines key aspects and challenges of different wafer reconstruction process flows. Based on analytical and finite element method modeling, guidelines for material selection and structural design are generated. One selected process flow is successfully demonstrated in a typical 300 mm eWLB production environment, proving the feasibility of wafer reconstruction as a 3D integration process flow.
  • Keywords
    finite element analysis; integrated circuit packaging; three-dimensional integrated circuits; 3D integration process flow; bumping; die-to-wafer assembly; eWLB production environment; finite element method modeling; integral handle-able wafer; material selection; redistribution layer deposition; size 300 mm; structural design; wafer reconstruction process flows; Analytical models; Electromagnetic compatibility; Finite element analysis; Semiconductor device modeling; Silicon; Three-dimensional displays;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Electronics Packaging Technology Conference (EPTC 2013), 2013 IEEE 15th
  • Conference_Location
    Singapore
  • Print_ISBN
    978-1-4799-2832-3
  • Type

    conf

  • DOI
    10.1109/EPTC.2013.6745754
  • Filename
    6745754