DocumentCode
3363553
Title
Design and comparison of CMOS Current Mode Logic latches
Author
Usama, Muhammad ; Kwasniewski, Tad
Author_Institution
Dept. of Electron., Carleton Univ., Ottawa, Ont., Canada
Volume
4
fYear
2004
fDate
23-26 May 2004
Abstract
A comprehensive study of the MOS Current Mode Logic (MCML) is presented. Operation of a conventional MCML latch is analyzed and some modified structures are described. A novel structure is proposed for increased stability with reduced delay parameters. General problems with single-ended to differential conversion are addressed. Comparative performance measures of Master-Slave (MS) latches are presented in a 0.18-μm CMOS technology.
Keywords
CMOS integrated circuits; current-mode logic; flip-flops; integrated circuit design; integrated circuit modelling; 0.18 micron; CMOS Current Mode Logic latches; CMOS technology; delay parameters; master-slave latches; single ended-differential conversion; CMOS logic circuits; CMOS technology; Clocks; Delay; Flip-flops; Frequency; Latches; Logic design; Timing; Voltage;
fLanguage
English
Publisher
ieee
Conference_Titel
Circuits and Systems, 2004. ISCAS '04. Proceedings of the 2004 International Symposium on
Print_ISBN
0-7803-8251-X
Type
conf
DOI
10.1109/ISCAS.2004.1329013
Filename
1329013
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