Improving the acquisition time of a PLL-based, integer-N frequency synthesizer

A Phase-Locked Loop-based frequency synthesizer switches between channels as the feedback division ratio is changed. For a given spectral purity, the acquisition time is often the bottleneck in the design of integer-N synthesizers. This paper presents a review of the three major phases of the total acquisition time from control systems theory and PLL literature. These are the pull-in time, the settling-time and the lock-time. An implementation example in a 0.25 μm CMOS process illustrates the process of reduction of the acquisition time by a factor of 3.5 for an integer-N synthesizer.