A novel 1.5 V CMFB CMOS down-conversion mixer design for IEEE 802.11 A WLAN systems

Author

Wang, Xuezhen ; Weber, Robert ; Chen, Degang

Author_Institution

Dept. of Electr. & Comput. Eng., Iowa State Univ., Ames, IA, USA

Volume

4

fYear

2004

fDate

23-26 May 2004

Abstract

This paper presents a 5.8 GHz low voltage down-conversion mixer design integrated in a TSMC 0.18 μm CMOS process. The proposed method features that an RF input stage converts the RF input voltage to current, which is coupled to the core of Gilbert Cell using current mirror. This implementation eliminates the current source transistor at bottom and furthermore reduces the supply voltage. Common-mode feedback is used for the active load of the mixer. The LO frequency is at 5.6 GHz. The designed mixer requires only a 1.5 V supply voltage and consumes 11.78 mW DC power. At 5.8 GHz, this mixer has single-sideband noise figure (SSB NF) of 13.6 dB, with input return loss of -18 dB, with output return loss of -26.4 dB, Third-order Input Intercept Point (IIP3) of -10.66 dBm, and conversion gain of 10.4 dB.

Keywords

CMOS integrated circuits; integrated circuit design; integrated circuit modelling; integrated circuit noise; mixers (circuits); radiofrequency integrated circuits; wireless LAN; -18 dB; -26.4 dB; 0.18 micron; 1.5 V; 10.4 dB; 11.78 mW; 13.6 dB; 5.6 GHz; 5.8 GHz; CMFB CMOS down-conversion mixer design; CMOS process; DC power; Gilbert Cell; RF input stage; RF input voltage; TSMC; WLAN systems; common mode feedback; conversion gain; current mirror; current source transistor; single-sideband noise figure; third-order input intercept point; Amplitude modulation; CMOS process; Feedback; Low voltage; Mirrors; Mixers; Noise figure; Noise measurement; Radio frequency; Wireless LAN;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems, 2004. ISCAS '04. Proceedings of the 2004 International Symposium on

Print_ISBN

0-7803-8251-X

Type

conf

DOI

10.1109/ISCAS.2004.1329018

Filename

1329018