Misalignment of the Block Oxide Height in Self-Aligned bSPIFET

For the purpose of performance improvement from bSPIFET (Si on partial insulator with block oxide field-effect transistor) technology [1], a self-aligned bSPIFET was proposed. However, a lot of electrical characteristics have not yet been studied in detail. This paper aims to investigate the device behaviour of self-aligned bSPIFET as a function of misaligned block oxide height. According to the TCAD simulation, the misalignment of the block oxide height makes the fluctuation in electrical characteristics (e.g., drain-induced barrier lowering DIBL, subthreshold swing, leakage current), hence the etch rate of oxide for the block spacer formation becomes one of the key parameters for self-aligned bSPIFET process. This is due to the block oxide height enclosing the Si-body, which decides the blocked regions between body and source/drain (S/D). In brief, the main function of the block oxide is to diminish the charge sharing for improving the device performance.