A 5-bit Interpolating Flash ADC in 0.13-μm SiGe BiCMOS

Author

Chen, Po-Hsin ; Peckerar, Martin

Author_Institution

Maryland Univ., College Park

fYear

2007

fDate

May 30 2007-June 1 2007

Firstpage

1

Lastpage

3

Abstract

In this paper, the interpolating comparator technique is shown to reduce the power dissipation of a flash ADC. We report on the design of a S-bit interpolating flash converter to validate our assertion. The ADC has been simulated in a 0.13-μm 2.5-V SiGe BiCMOS technology. The total static power dissipation is 66.14 mW. This is half the power dissipation incurred by a conventional full-flash converter of similar design. No apparent performance penalty was incurred. The linearity performance achieves a differential nonlinearity (DNL) of 0.114 LSB and an integral nonlinearity (INL) of 0.076 LSB at 2-GSample/s with an ENOB of 4.3 bits.

Keywords

CMOS integrated circuits; analogue-digital conversion; elemental semiconductors; germanium; silicon; 5-bit interpolating flash; BiCMOS technology; S-bit interpolating flash converter; SiGe; differential nonlinearity; integral nonlinearity; interpolating comparator technique; power dissipation; size 0.13 micron; voltage 2.5 V; BiCMOS integrated circuits; Clocks; Germanium silicon alloys; Heterojunction bipolar transistors; Interpolation; Latches; Power dissipation; Preamplifiers; Silicon germanium; Virtual colonoscopy;

fLanguage

English

Publisher

ieee

Conference_Titel

Integrated Circuit Design and Technology, 2007. ICICDT '07. IEEE International Conference on

Conference_Location

Austin, TX

Print_ISBN

1-4244-0756-7

Electronic_ISBN

1-4244-0757-5

Type

conf

DOI

10.1109/ICICDT.2007.4299563

Filename

4299563