DocumentCode
3363785
Title
Design for testability to combat delay faults
Author
Savir, Jacob
Author_Institution
Dept. of Electr. & Comput. Eng., New Jersey Inst. of Technol., Newark, NJ, USA
fYear
1999
fDate
1999
Firstpage
407
Lastpage
411
Abstract
To successfully combat delay faults there is an urgent need for a proper design for testability (DFT). The foundation of any DFT methodology rests on its scan design. The paper describes a new design of a shift register latch that lends itself to distributed self-test and delay test. The advantages of this new SRL is faster application of test vectors, higher DC and AC fault coverages, with low performance impact. Operation, cost, and other attributes are studied in detail. Results of adopting this SRL are reported on ten pilot chips
Keywords
built-in self test; design for testability; logic CAD; shift registers; AC fault coverage; DFT methodology; SRL; delay faults; delay test; design for testability; distributed self-test; low performance impact; scan design; shift register latch; test vectors; Built-in self-test; Circuit faults; Circuit testing; Costs; Delay; Design for testability; Hardware; Latches; Protocols; Shift registers;
fLanguage
English
Publisher
ieee
Conference_Titel
Computer Design, 1999. (ICCD '99) International Conference on
Conference_Location
Austin, TX
ISSN
1063-6404
Print_ISBN
0-7695-0406-X
Type
conf
DOI
10.1109/ICCD.1999.808574
Filename
808574
Link To Document