An Efficient Design Procedure for High-Speed Low-Power Dual-Modulus CMOS Prescalers

Author

Desikachari, R. ; Steeds, M. ; Huard, J. ; Moon, U.

Author_Institution

Cambridge Silicon Radio, Cambridge

fYear

2007

fDate

11-14 Dec. 2007

Firstpage

645

Lastpage

648

Abstract

Dual-Modulus prescalers are high-speed blocks required for fractional PLL-based frequency synthesis. Besides the VCO, the prescaler is the other component that works at maximum frequencies and could often be the bottleneck in high-speed synthesizer design. This paper is an analysis of pulse-swallow prescalers and a design procedure that optimizes the speed and power for CMOS implementations. An 8/9 dual-modulus prescaler prototype IC was designed and fabricated in a 0.25 Â¿m process. Measured operating speed of 2.09 GHz is obtained while minimizing the total power consumption to 4.5 mWat 2.5V supply.

Keywords

CMOS integrated circuits; high-speed integrated circuits; dual-modulus CMOS prescaler; fractional PLL-based frequency synthesis; frequency 2.09 GHz; high-speed synthesizer design; power 45 mW; pulse-swallow prescaler; size 0.25 micron; voltage 2.5 V; Circuits; Design optimization; Feedback; Flip-flops; Frequency conversion; Frequency synthesizers; Signal synthesis; Silicon; Voltage; Voltage-controlled oscillators;

fLanguage

English

Publisher

ieee

Conference_Titel

Electronics, Circuits and Systems, 2007. ICECS 2007. 14th IEEE International Conference on

Conference_Location

Marrakech

Print_ISBN

978-1-4244-1377-5

Electronic_ISBN

978-1-4244-1378-2

Type

conf

DOI

10.1109/ICECS.2007.4511074

Filename

4511074