DocumentCode :
3363915
Title :
On the Scalability of Redundancy based SER Mitigation Schemes
Author :
Seifert, N. ; Gill, B. ; Zia, V. ; Zhang, M. ; Ambrose, V.
Author_Institution :
Intel Corp., Hillsboro
fYear :
2007
fDate :
May 30 2007-June 1 2007
Firstpage :
1
Lastpage :
9
Abstract :
A novel circuit-level simulation strategy to assess the impact of charge sharing on the upset rate of redundancy based radiation hardened designs is introduced. Accelerated measurements conducted at the Los Alamos National Laboratory show a 10s or better reliability of hardened latches over standard latches for 45nm and 90nm implementations. Despite this encouraging trend, our simulations project that compact redundancy hardened designs will have soft error rates similar to non-hardened designs within a few technology generations if no additional mitigation techniques are applied to reduce the impact of charge sharing.
Keywords :
circuit simulation; flip-flops; logic design; logic simulation; radiation hardening (electronics); redundancy; Los Alamos National Laboratory; SER mitigation; accelerated measurements; charge sharing; circuit-level simulation; latches reliability; redundancy based radiation hardened design; size 45 nm; size 90 nm; soft error rates; Circuit simulation; Clocks; Computational modeling; Error analysis; Latches; Radiation hardening; Random access memory; Redundancy; Scalability; Space technology; BISER; DICE; MBU; SER; SET; SEUT; charge sharing; radiation; redundancy; soft error;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Integrated Circuit Design and Technology, 2007. ICICDT '07. IEEE International Conference on
Conference_Location :
Austin, TX
Print_ISBN :
1-4244-0757-5
Electronic_ISBN :
1-4244-0757-5
Type :
conf
DOI :
10.1109/ICICDT.2007.4299573
Filename :
4299573
Link To Document :
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