Title :
A 10-bit, 1.8-GS/s Time-Interleaved Pipeline ADC
Author :
Hakkarainen, V. ; Rantala, A. ; Aho, M. ; Riikonen, J. ; Gomes-Martin, D. ; Åberg, M. ; Halonen, K.
Author_Institution :
Helsinki Univ. of Technol., Helsinki
Abstract :
In this paper, a 10-bit, 1.8-GS/s time-interleaved analog-to-digital converter (ADC) is presented. The ADC employs 24 parallel 10-bit pipeline ADCs to reach the conversion rate of 1.8 GS/s. Sampling clocks are generated by a delay-locked loop (DLL), which includes a calibration of timing skew. Offset and gain error are calibrated in order to overcome the effects of device mismatch within a channel ADC. The ADC, implemented with a 0.35-mum BiCMOS, achieves an effective number of bits (ENOB) of 7.19 bits with a 764-MHz input while consuming 3.5 W of power.
Keywords :
BiCMOS integrated circuits; analogue-digital conversion; clocks; delay lock loops; pipeline arithmetic; BiCMOS; analog-to-digital converter; delay-locked loop; frequency 764 MHz; power 3.5 W; sampling clocks; size 0.35 micron; time-interleaved pipeline ADC; timing skew; BiCMOS integrated circuits; Calibration; Capacitance; Clocks; Energy consumption; Pipelines; Sampling methods; Table lookup; Timing; Voltage;
Conference_Titel :
Electronics, Circuits and Systems, 2007. ICECS 2007. 14th IEEE International Conference on
Conference_Location :
Marrakech
Print_ISBN :
978-1-4244-1377-5
Electronic_ISBN :
978-1-4244-1378-2
DOI :
10.1109/ICECS.2007.4511081
